1. Field
Robust stacked via in substrate and printed circuit board (“PCB”) with interlocked structure within, more particularly the use and manufacturing of a stack via interconnect that prevents delamination.
2. Background
As the size of semiconductor devices decreases, the density of the circuit elements on the semiconductor device increases, and the interconnect density within the substrate and printed circuit board (“PCB”) increases. In order to achieve high density interconnect in the limited space, vias at different layer may be stacked together in a column structure. In substrate and PCB, multiple interconnect layers may be fabricated so that the conductive interconnect layers are separated by dielectric layers. A stacked via in a semiconductor substrate or PCB can provide an electrical connection between conductors on different layers of the substrate or PCB. During manufacturing, packaging, attachment, rework and use condition, the stack via interconnect may experience thermal variation and vertical tensile strain due to the mismatch of coefficient of thermal expansion (“CTE”) between stack via interconnect, dielectric and conductor. Therefore, it is desirable to manufacture a stack via that can avoid being damage or delaminating within the column structure which if broken could lead to electrical failure.